Semiconductor memories are constructed from memory cells that are arrayed into rows and columns to form a large array of thousands or millions of cells. Standard static or dynamic-random-access memory (RAM) cells each store one bit of data that can be read or written as needed.
A more specialized memory cell is sometimes needed. One specialized memory is a content-addressable memory (CAM). In addition to the RAM functions of writing and storing data, the CAM also tests or compares the stored data to determine if the data matches test data applied to the memory. When the newly-applied test data matches the data already stored in the memory, a match line is activated, indicating that the stored data matches the test data. CAMs are especially useful for fully-associative memories such as look-up tables and memory-management units.
Each CAM cell is essentially a RAM cell with a match function. Match functions can be implemented by adding an exclusive-OR (XOR) or inverse XOR gate to each RAM cell. The XOR output is applied to a match line that connects many CAM cells together in a row or column. The match signal can then be output from the memory.
CAM cells were originally constructed from static RAM (SRAM) cells by adding transistors to perform the XOR function. More recently, CAM cells have also been constructed from dynamic RAM (DRAM) cells. DRAM cells have an area and cost advantage over SRAM cells since a small capacitor stores charge rather than a bi-stable or cross-coupled pair of transistors.
Dynamic Cam Cells--FIG. 1
FIG. 1 shows a prior-art dynamic CAM cell using six transistors. U.S. Pat. No. 5,428,564 by Winters shows a six-transistor (6T) CAM cell based on earlier dynamic CAM cells of just 4 or 5 transistors. While the earlier 4T and 5T CAM cells were small in area, these cells were particularly noise sensitive and slow, having relatively low voltage ratios.
Winter's CAM cell is written by raising the voltage on the write line, which activates pass transistors 12, 14. True and complement data are applied to bit lines BL and BLB, which are passed through pass transistors 12, 14 to store charge on the gates of storage transistors 18, 16. The sources of storage transistors 16, 18 are also connected to bit lines BL, BLB so that an additional voltage difference from gate to source is created, increasing the stored charge. For example, when BL is high and BLB is low, the high voltage from BL is transmitted to the gate of storage transistor 18, while the low voltage from BLB is applied to the source of storage transistor 18. At the same time, the low voltage from BLB is transmitted to the gate of storage transistor 16, while the high voltage from BLB is applied to the source of storage transistor 16. Thus storage transistors 16, 18 are charge oppositely during a write. Inverse read signal RD-NOT is high during write, and diode transistor 10 stays off so that the drains of storage transistors 16, 18 do not discharge the bit lines.
During a read, signal RD-NOT is low, and diode transistor 10 pulls low the drains of storage transistors 16, 18. One of bit lines BL, BLB is pulled low, depending on which of storage transistors 16, 18 has its gate charged high during the last write. The cell's data can then be read as a voltage difference across the bit lines using a sense amplifier. The CAM cell can be periodically refreshed by reading and then writing back the data to the cell.
During a compare or match operation, match line MATCH and RD-NOT are high and WRITE is low. The bit lines BL and BLB are precharged low. One of the bit lines is then pulled high with the test data. When the test data matches the stored data, storage transistor 16 or 18 connected to the raised bit line is off, preventing the drains from being charged high. The low voltage is applied to the gate of match transistor 20, which does not turn on, keeping MATCH high. When the test data mismatches the stored data, the storage transistor 16 or 18 connected to the raised bit line is turned off, charging high the drains of storage transistors 16, 18. The high drain voltage is applied to the gate of match transistor 20, turning it on, discharging MATCH low.
Winter's CAM cell uses only n-channel (NMOS) transistors, and has a small area. However, bit-line capacitance is high, since the sources of storage transistors 16, 18 are connected directly to the bit lines, as are pass transistors 12, 14. The high bit-line capacitance slows read and write operations. Also, there is the danger of sub-threshold leakage through storage transistors 12, 14 and of disturbance of the storage node from the bit lines. Another disadvantage is the layout efficiency in the MATCH/WL direction. The pitch in this direction may be greater than desired. The gate voltage of transistor 20 can only go as high as VCC-Vt; thus its current drive is weak.
CMOS Dynamic Cam Cell--FIG. 2
FIG. 2 is a prior-art dynamic CAM cell using CMOS transistors. See U.S. Pat. No. 4,791,606 by Threewitt et al. A single bit of data is stored on capacitor 28 when pass transistor 22 is activated by word line WL. Only one bit line BL is used.
An XOR gate is formed by n-channel transistors 24, 28 and p-channel transistors 21, 23. The stored data from capacitor 28 is applied to the gates of transistors 23, 26, while the bit line BL drives the gates of transistors 21, 24. The source of n-channel transistor 26 and the drain of n-channel transistor 23 are driven by mask line MASK, which is pulled low when the CAM cell is being compared. MASK can be pulled high to mask off or disable some cells from being compared. The drain of n-channel transistor 24 and the source of n-channel transistor 21 are connected to match line MATCH.
During a compare or match operation, the inverse data is applied to bit line BL, which is sometimes designated BL/CB to indicate that true data is applied during write, but complement data during compare. Word line WL is kept low so pass transistor 22 is off. Thus the stored data is applied to the gates of transistors 23, 26, while the complement of the test data is applied to the gates of transistors 21, 24 from the bit line. When the stored data and the complement driven to BL do not match, one of transistors 24, 26 in series is on and the other is off. Likewise, one of transistors 21, 23 is on and the other is off. Thus neither series connection has both transistors on, and the match line is not discharged low to MASK, which is driven low during compare. Thus a match is signaled.
When the stored data does match the complement data on BL, the match line is pulled low (a mis-match). If the stored data is high and BL is high, n-channel transistors 24, 26 are both on but p-channel transistors 21, 23 are both off. MATCH is discharged through n-channel transistors 24, 26. For low stored data and BL low, p-channel transistors 21, 23 discharge MATCH.
While such a CMOS CAM cell is useful, integrating p-channel transistors 21, 23 into each cell is expensive. The spacing from a p-channel transistor to an n-channel transistor is large, since separate P and N wells must be made. The spacing between two n-channel transistors is much smaller. Thus the size of the cell is larger when p-channel transistors are included with the n-channel transistors. Also, a single bit line makes reading and writing slow since an absolute voltage rather than a voltage difference is sensed or driven.
Pull MATCH low is a problem using the P-channel transistors. These devices can only be pulled to VSS+Vt. For low-voltage operation, performance may be severely affected. Also, for the same drive strength, the P-devices must be about twice the size of the N-devices. Also, the cell cannot be read.
What is desired is a CAM cell using only n-channel transistors. It is desired to use dynamic storage rather than static storage to reduce the size of the CAM cell. A dynamic CAM cell is desired that contains only NMOS transistors. A compact layout for an NMOS dynamic CAM cell is also desired.